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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.1
- 발행연도
- 2019.2
- 수록면
- 97 - 108 (12page)
- DOI
- 10.5573/JSTS.2019.19.1.097
이용수
초록· 키워드
오류제보하기
This paper presents a delay and area optimized multifunction unit with a wide operation set of matrix, vector, and elementary functions for mobile and wearable GPU shaders. The proposed unit unifies 25 non-trivial arithmetic operations on its single four-way arithmetic hardware. It employs two programmable modules for the unification of its operations. Novel unification architectures for these programmable modules are presented to optimize delay and area of the unit. Based on these architectures, the multifunction unit shows 10% and 3.5% reductions in its delay and area, respectively, compared with the prior art.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. MULTIFUNCTION UNIT
Ⅲ. EVALUATION RESULTS
Ⅳ. CONCLUSION
REFERENCES
참고문헌 (8)
참고문헌 신청
Khronos Group, OpenGL-ES 2.0, 3.0, available at http://www.khronos.org.
E. Lindholm, M. J. Kilgard, H. Moreton, A User- Programmable Vertex Engine, Proc. SIGGRAPH 2001, pp. 149-158, Aug. 2003.
B.-G. Nam, H. Kim, and H.-J. Yoo, Power and Area Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems, IEEE Trans. Computers, vol. 57, no. 4, pp. 490-504, Apr. 2008.
B.-G. Nam and H.-J. Yoo, An Embedded Stream Processor Core based on Logarithmic Arithmetic for a Low-Power 3D Graphics SoC, IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1554-1570, May 2009.
J. N. Mitchell Jr., Computer Multiplication and Division Using Binary Logarithms, IRE Trans. Electronic Computers, vol. 11, pp. 512-517, Aug. 1962.
B.-G. Nam, H. Kim, and H.-J. Yoo, Power and Area Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems, IEEE Trans. Computers, vol. 57, no. 4, pp. 490-504, Apr. 2008.
B.-G. Nam and H.-J. Yoo, An Embedded Stream Processor Core based on Logarithmic Arithmetic for a Low-Power 3D Graphics SoC, IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1554-1570, May 2009.
J. N. Mitchell Jr., Computer Multiplication and Division Using Binary Logarithms, IRE Trans. Electronic Computers, vol. 11, pp. 512-517, Aug. 1962.
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UCI(KEPA) : I410-ECN-0101-2019-569-000425935