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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.18 No.3
- 발행연도
- 2018.6
- 수록면
- 321 - 327 (7page)
- DOI
- 10.5573/JSTS.2018.18.3.321
이용수
초록· 키워드
오류제보하기
The transient response of the negative capacitance (NC) in a P(VDF<SUB>0.75</SUB>-TrFE<SUB>0.25</SUB>) ferroelectric capacitor is experimentally compared against that of a P(VDF<SUB>0.50</SUB>-TrFE<SUB>0.50</SUB>) ferroelectric capacitor. To measure first-hand the negative capacitance of the capacitor, a basic resistor-capacitor (RC) series circuit consisting of an external resistor and the ferroelectric capacitor was constructed. It was verified that the time duration of the NC could be adjusted based on the value of the external resistor. It was also confirmed that the transient response of the NC of the P(VDF<SUB>0.75</SUB>-TrFE<SUB>0.25</SUB>) ferroelectric capacitor versus that of the P(VDF<SUB>0.50</SUB>-TrFE<SUB>0.50</SUB>) ferroelectric capacitor was more sensitive to variation in the external resistor values. This is attributed to the reason that the polarization switching of P(VDF<SUB>0.75</SUB>-TrFE<SUB>0.25</SUB>) ferroelectric capacitor is faster than that of the P(VDF<SUB>0.50</SUB>-TrFE<SUB>0.50</SUB>) ferroelectric capacitor.
목차
Abstract
I. INTRODUCTION
II. FABRICATION AND MEASUREMENT
III. RESULTS AND DISCUSSION
IV. CONCLUSION
REFERENCES
참고문헌 (20)
참고문헌 신청
H. Nam, G. S. Lee, H. Lee, I. J. Park, and C. Shin, “Analysis of random variations and variationrobust advanced device structures,” Journal of Semiconductor Technology and Science, vol. 14, no. 1, pp.8-22, Feb. 2014. DOI: 10.5573/JSTS.2014. 14.1.008
G. S. Lee and C. Shin, “Computing-inexpensive matrix model for estimating the threshold voltage variation by workfunction variation in highk/ metal-gate MOSFETs,” Journal of Semiconductor Technology and Science, vol. 14, no. 1, pp. 96-99, Feb. 2014. DOI: 10.5573/JSTS.2014.14. 1.096
I. J. Park and C. Shin, “Monte Carlo simulation study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs,” Journal of Semiconductor Technology and Science, vol. 13, no. 5, pp. 511-515, Oct. 2013.
H. Nam, S. Park, and C. Shin, “Performance and variation-immunity benefits of segmented-channel MOSFETs (SegFETs) using HfO2 and SiO2 trench isolation,” Journal of Semiconductor Technology and Science, vol. 14, no. 4, pp. 427-435, Aug. 2014. DOI: 10.5573/JSTS.2013.13.5.511
W. Kwon, I. J. Park, and C. Shin, “Highly scalable NAND flash memory cell design embracing backside charge storage,” Journal of Semiconductor Technology and Science, vol. 15, no. 2, pp. 306-311, Apr. 2015. DOI: 10.5573/JSTS.2015. 15.2.286
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