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논문 기본 정보

자료유형
학술저널
저자정보
Natsuyuki Koda (The University of Shiga Prefecture) Furuichi Kosuke (The University of Shiga Prefecture) Hiromu Uemura (The University of Shiga Prefecture) Hiromi Inaba (The University of Shiga Prefecture) Keiji Kishine (The University of Shiga Prefecture)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.6
발행연도
2017.12
수록면
733 - 741 (9page)
DOI
10.5573/JSTS.2017.17.6.733

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초록· 키워드

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This paper proposes a simple and low power highly sensitive frequency demodulator. In the previous work, we proposed a multiplex communication system that transmits additional data by using a frequency modulation technique and the proposed circuit provided highly sensitive characteristics on frequency demodulation. However, with this configuration, there is the problem that the power consumption and the number of control points increase. Therefore, in this paper, we propose a simple and lower power circuit configuration. We investigated the characteristics of these frequency demodulators using a prototype demodulation system consisting of an FPGA and discrete devices. Compared with the delay detection circuit, the proposed simple and lower power demodulation system, which showed the same output characteristics as the conventional sensitive demodulator, successfully detected about twice the detection data than the delay detection circuit did.

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Abstract
I. INTRODUCTION
II. LABELING SIGNAL SYSTEM
III. IMPROVEMENT OF HIGHLY SENSITIVE FREQUENCY DEMODULATOR CIRCUIT
IV. MEASUREMENT RESULTS
V. CONCLUSION
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UCI(KEPA) : I410-ECN-0101-2018-569-001737869