지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.5
- 발행연도
- 2017.10
- 수록면
- 666 - 674 (9page)
- DOI
- 10.5573/JSTS.2017.17.5.666
이용수
초록· 키워드
오류제보하기
This paper proposes a modulator that improves the signal-to-noise and distortion ratio (SNDR) by 6 dB compared with the conventional modulator. A high pass dither shaper added to the raised modulator eliminates harmonic spurs without increasing the in-band noise floor. Moreover, a behavior-level modeling method is proposed for a 200 KHz bandwidth switch-capacitor sigma-delta digital to analog converter (SC ΣΔDAC). Consequently, by considering the main non-idealities in the SC ΣΔDAC, in contrast with the conventional SC ΣΔDAC, MATLAB simulation results show that the SC ΣΔDAC with the proposed modulator boosts the SNDR by approximately 6 dB and the spurious free dynamic range (SFDR) by approximately 8 dB. Finally, with the circuit implemented in a 0.18 μm CMOS process, the measurement results are also used to further validate the proposed SC ΣΔDAC model.
목차
Abstract
I. INTRODUCTION
II. DESIGN AND BEHAVIORAL MODELING
III. MAJOR NON-IDEALITIES IN THE SC ΣΔDAC
IV. VALIDATION OF THE PROPOSED MODEL
V. CONCLUSIONS
REFERENCES
참고문헌 (23)
참고문헌 신청
Kim, Si-Nai, et al, “A 6-bit 3.3GS/s Current- Steering DAC with Stacked Unit Cell Structure”, Journal of Semiconductor Technology and Science, Vol.12, No.3, pp.270-277, Sep., 2012.
Kim, Binheeim, et al, “A 40fJ/c-s 1 V 10 bit SARADC with Dual Sampling Capacitive DAC Topology”, Journal of Semiconductor Technology and Science, Vol.11, No.1, pp.23-32, Mar., 2011.
R. Schreier, G. C. Temes, Understnding Delta- Sigma Data Converters. IEEE press Piscataway, NJ, 2005.
Yongjian Tang, et al, “A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping”, IEEE Journal of Solid-State Circuits, Vol.46, No.6, pp.1371-1381, Jue., 2011.
K. Nguyen, A. Bandyopadhyay, B. Adams, et al, “A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique”, IEEE Journal of Solid-State Circuits, Vol.43, No.12, pp.2592-2600, Dec., 2008.
Yongjian Tang, et al, “A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping”, IEEE Journal of Solid-State Circuits, Vol.46, No.6, pp.1371-1381, Jue., 2011.
K. Nguyen, A. Bandyopadhyay, B. Adams, et al, “A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique”, IEEE Journal of Solid-State Circuits, Vol.43, No.12, pp.2592-2600, Dec., 2008.
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