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논문 기본 정보

자료유형
학술저널
저자정보
Abbas Syed Hayder (Sungkyunkwan University) Young-Jun Park (Sungkyunkwan University) SangYun Kim (Sungkyunkwan University) Young-Gun Pu (Sungkyunkwan University) Sang-Sun Yoo (Sungkyunkwan University) Youngoo Yang (Sungkyunkwan University) Minjae Lee (Gwangju Institute of Science and Technology) Keum Choel Hwang (Sungkyunkwan University) Kang-Yoon Lee (Sungkyunkwan University)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.17 No.3
발행연도
2017.5
수록면
821 - 834 (14page)

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초록· 키워드

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This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

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Abstract
I. INTRODUCTION
II. PROPOSED ARCHITECTURE
III. DIGITAL CONTROL STAGE
IV. EXPERIMENTAL RESULTS
V. CONCLUSIONS
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