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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.6
- 발행연도
- 2014.12
- 수록면
- 824 - 831 (8page)
이용수
초록· 키워드
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In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. SIMULATION SETUP
Ⅲ. SIMULATION RESULTS
Ⅳ. CONCLUSION
REFERENCES
참고문헌 (27)
참고문헌 신청
1. [인터넷자원] - / / International Technology Roadmap for Semiconductors (ITRS)
2. [학술지(정기간행물)] - A. B. Kahng / 2010 / Layout Decomposition Approaches for Double Patterning Lithography / IEEE Transactions on CAD of Integrated Circuits and Systems 29 (6) : 939 ~ 952
3. [학술지(정기간행물)] - K. Yuan / 2010 / Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization / IEEE Transactions on CAD of Integrated Circuits and Systems 29 (2) : 185 ~ 196
4. [학술대회논문] - G. Luk-Pat / 2008 / Printability Verification for Double-Patterning Technology / Proc. of SPIE 7122, Photomask Technology
5. [학술대회논문] - C. Cork / 2008 / Comparison of Triple-Patterning Decomposition Algorithms Using Aperiodic Tiling Patterns / Proc. of SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV 7028 : 39.1 ~ 39.7
2. [학술지(정기간행물)] - A. B. Kahng / 2010 / Layout Decomposition Approaches for Double Patterning Lithography / IEEE Transactions on CAD of Integrated Circuits and Systems 29 (6) : 939 ~ 952
3. [학술지(정기간행물)] - K. Yuan / 2010 / Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization / IEEE Transactions on CAD of Integrated Circuits and Systems 29 (2) : 185 ~ 196
4. [학술대회논문] - G. Luk-Pat / 2008 / Printability Verification for Double-Patterning Technology / Proc. of SPIE 7122, Photomask Technology
5. [학술대회논문] - C. Cork / 2008 / Comparison of Triple-Patterning Decomposition Algorithms Using Aperiodic Tiling Patterns / Proc. of SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV 7028 : 39.1 ~ 39.7
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UCI(KEPA) : I410-ECN-0101-2016-569-001112608