지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 294 - 297 (4page)
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초록· 키워드
오류제보하기
With the increasing demand for higher bandwidth, network operators are updating their devices to support 40GE/100GE standards. Besides, next generation 400GE and 1TE standards are also in discussion, which pose big challenges to network chip design. Packet processing, packet buffering, switch fabric and chip interfaces are main challenges in network chip design. Among them, packet buffer might be the top problem because of the well known “Memory Wall”. IBM solves the problem by providing a highly efficient chip interface, innovative memory technologies and advanced design process. In this paper, we address the bottleneck of the traffic manager chips which perform high performance packet buffering. Based on the analysis, we show how to solve the chip implementation difficulties to meet next generation bandwidth requirements.
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Abstract
Introduction
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Summary
References
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UCI(KEPA) : I410-ECN-0101-2016-569-001049091