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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 237 - 240 (4page)
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초록· 키워드
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An architecture is proposed to design a single chip with an application processor (AP) and a modem processor (MP). As an aggressive challenge, the MP’s dedicated memory is removed to share the main memory with the AP. In addition, an autonomous power management (APM) is presented to reduce the power consumption of time-constrained tasks such as wireless communication. The APM is designed without the intervention of the microprocessors, to deal with the random and sparse data pattern of voice communication. For the architectural exploration, an electronic system-level simulation is performed for verifying the performance and power consumption. Through the simulation results, the proposed architecture exhibits small size, good performance and energy consumption.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. APPLICATION PROCESSOR INTEGRATED WITH MODEM PROCESSOR
Ⅲ. ARCHITECTURAL EXPLORATION WITH VIRTUAL PLATFORM
Ⅳ. SIMULATION RESULTS
Ⅴ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2016-569-001048943