지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 154 - 157 (4page)
이용수
초록· 키워드
오류제보하기
The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture. The full version of the paper can be found at [1].
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. BACKGROUND
Ⅲ. STATIC MEMORY ACCESS PATTERN ANALYSIS
Ⅳ. ALGORITHMICALLY SELECTING THREAD MAPPINGS AND WORK GROUP SIZES
Ⅴ. EXPERIMENTAL RESULTS AND CONCLUSION
REFERENCES
참고문헌 (0)
참고문헌 신청이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2016-569-001048701