지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 99 - 102 (4page)
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초록· 키워드
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This paper presents a clock generator featuring a feedback temperature and voltage compensation circuit and low dropout regulator circuit on-chip capable of constraining frequency variation to 3.49 %. The inclusion of an OPA, MOS transistors and resistors eliminates the need of large BJT devices to reduce the area penalty and achieve low power consumption. Particularly, a negative feedback temperature compensation bias circuit utilizes only a MOS transistor and a resistor to improve compensation capability. The proposed design is implemented using TSMC 0.18 ㎛ CMOS process followed by simulation in the temperature range between of 0 ℃ to 100 ℃. The post-layout-extracted simulation results reveal that the worstcase error is less than 2 ㎷ with calibration, which is 72 % improvement compared with the state of art.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. TEMPERATURE AND VOLTAGE COMPENSATION CLOCK GENERATOR
Ⅲ. IMPLEMENTATION AND SIMULATION RESULTS
Ⅳ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2016-569-001048554