지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 56 - 59 (4page)
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초록· 키워드
오류제보하기
In the pre-concept phase of system-on-chip (SoC) design, generally early architectural exploration and optimization is performed with the abstract level models, which provides throughput numbers with accuracy 10-15%. Conventionally FPGA or emulator based evaluation is done in design cycle to provide more accurate numbers, but it comes at a late stage of the design. In today’s low time to market (6-8 months tapeout), it would be intolerable to fine tune the architecture/design parameters based on emulator results. To get more accurate estimation at early design stage, an attempt is made to run the critical use-case (end-to-end) scenarios in functional verification on the SoC RTL before building any emulator or FPGA based setup. The early feedback from this simulation helps in fine tuning the design to achieve the required results. In this paper we propose a methodology and SoC testbench framework for running custom use-case (or any standard benchmark) based performance simulation (at RTL level) which optimizes simulation time in the order of 10X or more. And the impact of it is also discussed. The performance prediction done with this methodology is very closely matching with (~98%) the actual performance achieved on silicon for C293 [1].
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. AREA OF PERFORMANCE EVALUATION
Ⅲ. TYPICAL USE-CASE
Ⅳ. PROPOSED TESTBENCH FRAMEWORK
Ⅴ. PERFORMANCE SIMULATION RESULTS
Ⅵ. CONCLUSION
References
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UCI(KEPA) : I410-ECN-0101-2016-569-001048423