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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 19 - 22 (4page)
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초록· 키워드
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This paper proposes the pipeline clock network design for recent three-dimensional (3D) VLSI system. The multi-layer processor chip can be connected by Through-Silicon Via (TSV) tunnels. The multi-clock VLSI system can also enhance whole VLSI system performance for better design flexibility. The pipeline clock network is determined by inserted buffer control. Different size buffers in different layers can realize fast system operation and zero-skew clock signals. Whole VLSI processor speed can be increased rapidly, and 3D chip size can also be reduced greatly by 3D pipeline clock network design. System clock routing efficiency can also be improved because 3D clock tree can avoid most parts of the obstacle elements. Experimental results can be used to prove that 3D pipeline clock network has better performance with fast operation speed and small routing length. VLSI system power can be reduced because of minimal routing distance in 3D network design.
목차
Abstract
Ⅰ. Introduction
Ⅱ. 3D multi-clock VLSI architecture
Ⅲ. 3D Pipeline Clock Network Architecture
Ⅳ. 3D Clock Integrity Signal Module
Ⅴ. 3D Clock Network Results and Discussions
Ⅵ. Conclusion and Future Work
References
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UCI(KEPA) : I410-ECN-0101-2016-569-001048327