As the number of ECUs increases, the complexity of vehicle E/E architecture also increases resulting in high cost and potential reliability issues. Combining few ECUs into one multi-core processor is desired to resolve the cost and the reliability issues. The proper use of a multi-core processor, however, requires a sophisticated software architecture that considers timing requirements and constraints of AUTOSAR and core-to-core communications. This paper describes how to the design a software architecture in a multi-core processor environment, to meet the timing requirements of optimizing the allocation of tasks on different cores and minimizing the core-to-core communications.