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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.3
- 발행연도
- 2014.6
- 수록면
- 322 - 330 (9page)
이용수
초록· 키워드
오류제보하기
New effective techniques to repair “small” design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many “small” errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timingcritical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many “small” errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. FAST AND LOW-COST POST-SILICON REPAIR
Ⅲ. PARTITIONING FOR REPAIRABILITY
Ⅳ. PSEUDO-INTERCONNECTION AND PSEUDOCELL TECHNIQUES DURING PHYSICAL DESIGN
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. EXPERIMENTAL RESULTS
REFERENCES
참고문헌 (12)
참고문헌 신청
1. [학술대회논문] - M. Abramovici / 2006 / A Reconfigurable Design-for-Debug Infrastructure for SoCs / Proc. DAC ’06 : 7 ~
2. [기타자료] - / 2005 / Collett International Research 2005
3. [학술대회논문] - T. Jhaveri / 2009 / OPC Simplification and Mask Cost Reduction Using Regular Design Fabrics / SPIE Proceedings 7274
4. [보고서] - Z. Or-Bach / 2005 / Paradigm Shift in ASIC Technology
5. [학술대회논문] - K. Chang / 2008 / Reap What You Sow: Spare Cells for Post-Silicon Metal Fix / Proc. ISPD'08 : 103 ~ 110
2. [기타자료] - / 2005 / Collett International Research 2005
3. [학술대회논문] - T. Jhaveri / 2009 / OPC Simplification and Mask Cost Reduction Using Regular Design Fabrics / SPIE Proceedings 7274
4. [보고서] - Z. Or-Bach / 2005 / Paradigm Shift in ASIC Technology
5. [학술대회논문] - K. Chang / 2008 / Reap What You Sow: Spare Cells for Post-Silicon Metal Fix / Proc. ISPD'08 : 103 ~ 110
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