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논문 기본 정보

자료유형
학술저널
저자정보
Peng Mao (Beijing Institute of Technology) Mao Zhang (Beijing Institute of Technology) Weiping Zhang (North China University of Technology)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.14 No.5
발행연도
2014.9
수록면
1,057 - 1,068 (12page)

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초록· 키워드

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Phase-locked loops (PLL) based on the synchronous reference frame (SRF-PLL) have recently become the most widely-used for grid synchronization in three phase grid-connected inverters. However, it is difficult to study their performance since they are nonlinear systems. To estimate the performances of a SRF-PLL, a canonical small-signal linearized model has been developed in this paper. Based on the proposed model, several significant specifications of a SRF-PLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth, and steady-state error have been investigated. Finally, a noise model of a SRF-PLL has been put forward to analyze the noise rejection ability by computing the SNR (signal-to-noise ratio) of a SRF-PLL. Several simulation and experimental results have been provided to verify and validate the obtained conclusions. Although the proposed model and analysis method are based on a SRF-PLL, they are also suitable for analyzing other types of PLLs.

목차

Abstract
I. INTRODUCTION
II. CONVENTIONAL SRF-PLL AND ITS SMALL?SIGNAL LINEARIZED MODEL
III. PERFORMANCE ANALYSIS OF THE SRF-PLL
IV. PERFORMANCE IN THE PRESENCE OF NOISE
V. CONCLUSIONS
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UCI(KEPA) : I410-ECN-0101-2015-500-002566750