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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.2
- 발행연도
- 2014.4
- 수록면
- 246 - 251 (6page)
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In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. CIRCUIT DESCRIPTION
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (9)
참고문헌 신청
1. [학술대회논문] - T. Sugiki / 2000 / A 60mW 10 b CMOS image sensor with column-to-column FPN reduction / Proc. IEEE ISSCC Dig. Tech. Papers : 108 ~ 109
3. [학술지(정기간행물)] - M. F. Snoeij / 2007 / Multiple-ramp column-parallel ADC architectures for CMOS image sensors / IEEE J. Solid-State Circuits 42 (12) : 2968 ~ 2967
4. [학술대회논문] - J. Lee / 2007 / A 10 b column-wise two-stage single-slope ADC for high-speed CMOS image sensor / Proc. IEEE Int. Image Sensor Workshop : 196 ~ 199
5. [학술대회논문] - Y. Nitta / 2006 / High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor / ISSCC Dig. Tech. Papers : 500 ~ 501
6. [학술지(정기간행물)] - Y. Yoshihara / 2006 / A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor with seamless mode change / IEEE J. Solid-State Circuits 41 : 2998 ~ 3006
3. [학술지(정기간행물)] - M. F. Snoeij / 2007 / Multiple-ramp column-parallel ADC architectures for CMOS image sensors / IEEE J. Solid-State Circuits 42 (12) : 2968 ~ 2967
4. [학술대회논문] - J. Lee / 2007 / A 10 b column-wise two-stage single-slope ADC for high-speed CMOS image sensor / Proc. IEEE Int. Image Sensor Workshop : 196 ~ 199
5. [학술대회논문] - Y. Nitta / 2006 / High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor / ISSCC Dig. Tech. Papers : 500 ~ 501
6. [학술지(정기간행물)] - Y. Yoshihara / 2006 / A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor with seamless mode change / IEEE J. Solid-State Circuits 41 : 2998 ~ 3006
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UCI(KEPA) : I410-ECN-0101-2015-560-001440648