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논문 기본 정보

자료유형
학술저널
저자정보
Junghyun Ham (Sungkyunkwan University) Haeryun Jung (Sungkyunkwan University) Hyungchul Kim (Sungkyunkwan University) Wonseob Lim (Sungkyunkwan University) Deukhyoun Heo (Washington State University) Youngoo Yang (Sungkyunkwan University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.2
발행연도
2014.4
수록면
235 - 245 (11page)

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This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

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Abstract
I. INTRODUCTION
II. CMOS POWER AMPLIFIER DESIGN
III. BIAS MODULATOR DESIGN
IV. ET PA CONFIGURATION AND MEASUREMENTS
V. CONCLUSIONS
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UCI(KEPA) : I410-ECN-0101-2015-560-001440633