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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.6
- 발행연도
- 2013.12
- 수록면
- 594 - 607 (14page)
이용수
초록· 키워드
오류제보하기
A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.
목차
Abstract
I. INTRODUCTION
II. COUPLED LINE ANALYSIS USING MODAL DECOUPLING
III. INPUT TEST PATTERNS IN A SINGLE LINE
IV. INPUT TEST PATTERNS IN COUPLED LINES
V. ACCURACY IMPROVEMENT IN THE MODEL
VI. VERIFICATION OF THE PROPOSED TECHNIQUE
VII. CONCLUSIONS
REFERENCES
참고문헌 (31)
참고문헌 신청
1. [인터넷자원] - / / International technology roadmap for semiconductors
2. [학술지(정기간행물)] - R. Nair / 2002 / Effect of increasing chip density on the evolution of computer architectures / IBM J. Res. & Dev. 46 (2) : 223 ~ 234
3. [학술지(정기간행물)] - R. Berridge / 2007 / IBM POWER6 microprocessor physical design and design methodology / IBM J. Res. & Dev. 51 (6) : 685 ~ 714
4. [학술지(정기간행물)] - N. Kurd / 2009 / Next generation Intel® coreTM micro-architecture (Nehalem) clocking / IEEE J. Solid-State Circuits 44 (4) : 1121 ~ 1129
5. [학술대회논문] - M. Bohr / 2009 / The new era of scaling in an SoC world / Proc. ISSCC : 23 ~ 28
2. [학술지(정기간행물)] - R. Nair / 2002 / Effect of increasing chip density on the evolution of computer architectures / IBM J. Res. & Dev. 46 (2) : 223 ~ 234
3. [학술지(정기간행물)] - R. Berridge / 2007 / IBM POWER6 microprocessor physical design and design methodology / IBM J. Res. & Dev. 51 (6) : 685 ~ 714
4. [학술지(정기간행물)] - N. Kurd / 2009 / Next generation Intel® coreTM micro-architecture (Nehalem) clocking / IEEE J. Solid-State Circuits 44 (4) : 1121 ~ 1129
5. [학술대회논문] - M. Bohr / 2009 / The new era of scaling in an SoC world / Proc. ISSCC : 23 ~ 28
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