지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.10
- 수록면
- 1,308 - 1,311 (4page)
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초록· 키워드
오류제보하기
A low pass filters (LPFs) are important building blocks for many analog integrated circuit design. The biomedical applications or the sensor applications require the LPFs with very low cut-off frequency. The simplest way to implement the LPF is using the passive RC filter. The passive RC LPF, however, consumes large chip area when the desired time constant is large. The transconductance-C (g<SUB>m</SUB>-C) filter or the switched capacitor (SC) filters are widely used to achieve the low cut-off frequency in limited area. However, non-linearity and switching noise are major drawbacks of the g<SUB>m</SUB>-C filters and the SC filters. This paper presents an area-efficient LPF using T-networked resistors and current-mode capacitance multiplier. The area of the proposed LPF is reduced to 8.31 % of the conventional passive RC LPF at the same cut-off frequency of 7.1 kHz. The proposed LPF is designed using standard 0.18 μm CMOS process with the option process of high-resistivity polysilicon resistor and metal-insulator-metal capacitor.
목차
Abstract
1. INTRODUCTION
2. CIRCUIT DESIGN
3. SIMULATION RESULT
4. CONCLUSION
REFERENCES
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