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논문 기본 정보

자료유형
학술저널
저자정보
Seongjoo Lee (Dongguk Univ) Jangwoo Lee (Dongguk Univ) Mun-Kyo Lee (Samsung Thales. Co.Ltd) Sun-Phil Nah (Defense Development) Minkyu Song (Dongguk Univ)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.5
발행연도
2013.10
수록면
473 - 481 (9page)

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초록· 키워드

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A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is 2.1 mm²(ADC core : 1.4 mm² , calibration engine : 0.7 mm²), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

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Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. CIRCUIT DESCRIPTION
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES

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UCI(KEPA) : I410-ECN-0101-2014-560-002740969