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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.5
- 발행연도
- 2013.10
- 수록면
- 423 - 429 (7page)
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초록· 키워드
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A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. CIRCUIT DESCRIPTION
IV. EXPERIMENTAL RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
1. [학술대회논문] - M. Green / 2003 / Design of CMOS CML circuits for high-speed broadband communications / Proc. IEEE Int. Symp. Circuits and Systems : 204 ~ 207
2. [학술대회논문] - D. Heidar / 2007 / Comparison of output drivers for high-speed serial links / Microelectronics, ICM 2007 : 329 ~ 337
3. [학술대회논문] - D. A. Yokoyama-Martin / 2006 / A multistandard low power 1.5-3.125Gb/s serial transceiver in 90nm CMOS / Proc. IEEE Custom Integrated Circuits Conf : 401 ~ 404
4. [학술지(정기간행물)] - J. Liu / 2004 / Equalization in high speed communication systems / IEEE Circuits and Systems Magazine, Second Quarter : 4 ~ 15
5. [학술지(정기간행물)] - K. Krishna / 2005 / A multigigabit backplane transceiver core in 0.13μm CMOS with a power-efficient equalization architecture / IEEE J. Solid-State Circuits 40 (12) : 2658 ~ 2666
2. [학술대회논문] - D. Heidar / 2007 / Comparison of output drivers for high-speed serial links / Microelectronics, ICM 2007 : 329 ~ 337
3. [학술대회논문] - D. A. Yokoyama-Martin / 2006 / A multistandard low power 1.5-3.125Gb/s serial transceiver in 90nm CMOS / Proc. IEEE Custom Integrated Circuits Conf : 401 ~ 404
4. [학술지(정기간행물)] - J. Liu / 2004 / Equalization in high speed communication systems / IEEE Circuits and Systems Magazine, Second Quarter : 4 ~ 15
5. [학술지(정기간행물)] - K. Krishna / 2005 / A multigigabit backplane transceiver core in 0.13μm CMOS with a power-efficient equalization architecture / IEEE J. Solid-State Circuits 40 (12) : 2658 ~ 2666
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