지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.4
- 발행연도
- 2013.8
- 수록면
- 331 - 341 (11page)
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초록· 키워드
오류제보하기
In the present work, the effect of the gate-to-drain capacitance (C<SUB>gd</SUB> on the noise performance of a symmetric tied-gate In <SUB>0.52</SUB>AI <SUB>0.48</SUB>As/In <SUB>0.53</SUB>Ga <SUB>0.47</SUB>As double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters (Y <SUB>11</SUB> and Y <SUB>21</SUB> which are obtained incorporating the effect of C <SUB>gd</SUB>, the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CHARGE CONTROL MODEL
Ⅲ. INFLUENCE OF GATE-TO-DRAIN CAPACITANCE
Ⅳ. INTRINSIC NOISE SOURCES
Ⅴ. NOISE PERFORMANCE PARAMETERS
Ⅵ. RESULTS & DISCUSSION
Ⅴ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-560-002404877