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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.4
- 발행연도
- 2013.8
- 수록면
- 272 - 281 (10page)
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초록· 키워드
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This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in 0.18㎛ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 3.5 ㎟. The power consumption of the ADPLL is 12.43 ㎽. And, the power consumptions of the transmitter are 35.36 ㎽ and 65.57 ㎽ when the output power levels are -1.6 ㏈m and +12 ㏈m, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ㎰. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 ㎐. The phase noise of the ADPLL output at 7.8㎓ is -121.17 ㏈c/㎐ with a 1㎒ offset.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. TRANSMITTER ARCHITECTURE
Ⅲ. BULLDING BLOCKS
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (9)
참고문헌 신청
1. [기타자료] - IEEE Draft Standard for Information technology / 2010 / Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs), P802.15.4g/D2
2. [학술지(정기간행물)] - M. H. Perrott / 1997 / A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation / IEEE J. Solid-State Circuits 32 (12) : 2048 ~ 2060
3. [학술지(정기간행물)] - R. B. Staszewski / 2005 / Phase-domain alldigital phase-locked loop / IEEE Trans. Circuits Syst. II, Expr. Briefs 52 (3) : 159 ~ 163
4. [학술지(정기간행물)] - V. Kratyuk / 2009 / A Digital PLL With a Stochastic Time-to-Digital Converter / IEEE Trans. Circuits Syst. I 56 (8) : 1612 ~ 1621
5. [학술지(정기간행물)] - Young-Hun Seo / 2011 / A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18- CMOS / IEEE Transactions on Circuits and Systems II: Express Briefs 58 (2) : 70 ~ 74
2. [학술지(정기간행물)] - M. H. Perrott / 1997 / A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation / IEEE J. Solid-State Circuits 32 (12) : 2048 ~ 2060
3. [학술지(정기간행물)] - R. B. Staszewski / 2005 / Phase-domain alldigital phase-locked loop / IEEE Trans. Circuits Syst. II, Expr. Briefs 52 (3) : 159 ~ 163
4. [학술지(정기간행물)] - V. Kratyuk / 2009 / A Digital PLL With a Stochastic Time-to-Digital Converter / IEEE Trans. Circuits Syst. I 56 (8) : 1612 ~ 1621
5. [학술지(정기간행물)] - Young-Hun Seo / 2011 / A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18- CMOS / IEEE Transactions on Circuits and Systems II: Express Briefs 58 (2) : 70 ~ 74
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