지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.3
- 발행연도
- 2013.6
- 수록면
- 259 - 262 (4page)
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초록· 키워드
오류제보하기
Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED ARCHITECTURE
Ⅲ. PERFORMANCE EVALUATION
Ⅳ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-560-003262604