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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.1
- 발행연도
- 2013.2
- 수록면
- 65 - 70 (6page)
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초록· 키워드
오류제보하기
A 0.18-μm 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.
목차
Abstract
I. INTRODUCTION
II. DEVICE STRUCTURE AND TCAD SIMULATION
III. IMPROVED EOS ROBUSTNESS
IV. CONCLUSIONS
REFERENCES
참고문헌 (8)
참고문헌 신청
1. [학술대회논문] - K. T. Kaschani / 2011 / The Impact of Electrical Overstress on the Design, Handling and Application of Integrated Circuits / EOS/ESD Symp. : 1 ~ 10
2. [학술대회논문] - J.-H. Kim / 2010 / A Consideration on the Electrical Overstress (EOS) Failure Mechanism in the Interconnection System of Liquid Crystal Display (LCD) Panel / Electronic Manuf. Tech. Symp. : 1 ~ 4
3. [학술지(정기간행물)] - M.-D. Ker / 2003 / Substrate-Triggered ESD Protection Circuit Without Extra Process Modification / Solid-State Circuits, IEEE Journal of 38 (2) : 295 ~ 302
4. [학술지(정기간행물)] - M.-D. Ker / 2008 / Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology / Electromagnetic Compatibility, IEEE Transactions on 50 (4) : 810 ~ 821
5. [학술지(정기간행물)] - J. E. Vinson / 2000 / Electrostatic Discharge in Semiconductor Devices: Protection Techniques / Proceedings of the IEEE 88 (12) : 1878 ~ 1900
2. [학술대회논문] - J.-H. Kim / 2010 / A Consideration on the Electrical Overstress (EOS) Failure Mechanism in the Interconnection System of Liquid Crystal Display (LCD) Panel / Electronic Manuf. Tech. Symp. : 1 ~ 4
3. [학술지(정기간행물)] - M.-D. Ker / 2003 / Substrate-Triggered ESD Protection Circuit Without Extra Process Modification / Solid-State Circuits, IEEE Journal of 38 (2) : 295 ~ 302
4. [학술지(정기간행물)] - M.-D. Ker / 2008 / Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology / Electromagnetic Compatibility, IEEE Transactions on 50 (4) : 810 ~ 821
5. [학술지(정기간행물)] - J. E. Vinson / 2000 / Electrostatic Discharge in Semiconductor Devices: Protection Techniques / Proceedings of the IEEE 88 (12) : 1878 ~ 1900
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