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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.1
- 발행연도
- 2013.2
- 수록면
- 22 - 27 (6page)
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초록· 키워드
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Detailed study on how the plasma process during the sidewall spacer formation suppresses the formation of silicide is done. In non-patterned wafer test, it is found that both fluorocarbon reactive ion etch (RIE) and TEOS plasma-enhanced deposition processes modify the Si surface so that the silicide reaction is chemically inhibited or suppressed. In order to investigate the cause of the chemical modification , we analyze the elements on the silicon surface through Auger Electron Spectroscopy (AES). From the AES result, it is found that the carbon induces chemical modification which blocks the reaction between silicon and nickel. Thus, protecting the surface from the carbon-containing plasma process prior to nickel deposition appears critical in successful silicide formation.
목차
Abstract
I. INTRODUCTION
II. EXPERIMENTAL
III. RESULTS AND DISCUSSION
IV. CONCLUSIONS
REFERENCES
참고문헌 (13)
참고문헌 신청
1. [학술지(정기간행물)] - T. Ohguro / 1994 / Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films / IEEE Transaction on Electron Devices : 2305 ~ 2317
2. [학술대회논문] - E. Morifuji / 2002 / High Performance 30 nm Bulk CMOS for 65 nm Technology Node (CMOS5) / IEEE International Electron Devices Meeting : 655 ~ 658
3. [학술대회논문] - J.P. Lu / 2002 / A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length / IEEE International Electron Devices Meeting : 371 ~ 374
4. [학술대회논문] - Qi Xiang / 2000 / Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi / 2000 Symposium on VLSI Technology. Digest of Technical Papers : 76 ~ 77
5. [학술대회논문] - A. Hokazono / 2002 / 14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide / IEEE International Electron Devices Meeting : 639 ~ 642
2. [학술대회논문] - E. Morifuji / 2002 / High Performance 30 nm Bulk CMOS for 65 nm Technology Node (CMOS5) / IEEE International Electron Devices Meeting : 655 ~ 658
3. [학술대회논문] - J.P. Lu / 2002 / A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length / IEEE International Electron Devices Meeting : 371 ~ 374
4. [학술대회논문] - Qi Xiang / 2000 / Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi / 2000 Symposium on VLSI Technology. Digest of Technical Papers : 76 ~ 77
5. [학술대회논문] - A. Hokazono / 2002 / 14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide / IEEE International Electron Devices Meeting : 639 ~ 642
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