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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Computing Science and Engineering Journal of Computing Science and Engineering Vol.6 No.4
- 발행연도
- 2012.12
- 수록면
- 267 - 278 (12page)
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초록· 키워드
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The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ASSUMED MULTICORE ARCHITECTURE
Ⅲ. COMPUTING THE WORST-CASE DELAY OF INTER-THREAD CACHE INTERFERENCES
Ⅳ. AN EXAMPLE OF USING CCCGS
Ⅴ. EVALUATION METHODOLOGY
Ⅵ. EXPERIMENTAL RESULTS
Ⅶ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000460169