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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.4
- 발행연도
- 2012.12
- 수록면
- 418 - 425 (8page)
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초록· 키워드
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In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CONVENTIONAL SEC-DED CODES
Ⅲ. ECC PROCESSING CIRCUITS
Ⅳ. CHECK BIT PRE-COMPUTATION
Ⅴ. PROPOSED SEC-DED CODE
Ⅵ. COMPARISON OF IMPLEMENTATION
Ⅶ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000667808