지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.4
- 발행연도
- 2012.12
- 수록면
- 397 - 404 (8page)
이용수
초록· 키워드
오류제보하기
Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. FLOORPLAN LEVEL BUFFER INSERTION
Ⅲ. THERMAL AWARE BUFFER INSERTION
Ⅳ. SIMULATION RESULTS
Ⅴ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (15)
참고문헌 신청
1. [학술지(정기간행물)] - C. Tsai / 2000 / Cell-level placement for improving substrate thermal distribution / Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 19 (2) : 253 ~ 266
2. [학술대회논문] - K. Sundaresan / 2008 / Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses / Quality Electronic Design, 2008, ISQED 2008. 9th International Symposium on : 118 ~ 122
3. [학술지(정기간행물)] - A. H. Ajami / 2005 / Modeling and analysis of nonuniform substratetemperature effects on global ULSI interconnects / Computer-Aided Design of Integrated Circuits andSystems, IEEE Transactions on 24 (6) : 849 ~ 861
4. [학술대회논문] - A. H. Ajami / 2001 / Analysis of substrate thermal gradient effects onoptimal buffer insertion / Computer Aided Design,2001, ICCAD 2001. IEEE/ACM InternationalConference on : 44 ~ 48
5. [학술대회논문] - K. Sundaresan / 2007 / An analysis of timing violations due to spatially distributed thermal effects in global wires / DAC 2007, In proceedings of the 44th annual Conference on : 515 ~ 520
2. [학술대회논문] - K. Sundaresan / 2008 / Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses / Quality Electronic Design, 2008, ISQED 2008. 9th International Symposium on : 118 ~ 122
3. [학술지(정기간행물)] - A. H. Ajami / 2005 / Modeling and analysis of nonuniform substratetemperature effects on global ULSI interconnects / Computer-Aided Design of Integrated Circuits andSystems, IEEE Transactions on 24 (6) : 849 ~ 861
4. [학술대회논문] - A. H. Ajami / 2001 / Analysis of substrate thermal gradient effects onoptimal buffer insertion / Computer Aided Design,2001, ICCAD 2001. IEEE/ACM InternationalConference on : 44 ~ 48
5. [학술대회논문] - K. Sundaresan / 2007 / An analysis of timing violations due to spatially distributed thermal effects in global wires / DAC 2007, In proceedings of the 44th annual Conference on : 515 ~ 520
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2014-569-000667777