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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.4
- 발행연도
- 2012.12
- 수록면
- 388 - 396 (9page)
이용수
초록· 키워드
오류제보하기
In this paper, a 320 × 240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13 ㎛ 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25 ㎛. The measured column fixed pattern noise (FPN) is 0.10 LSB.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE
Ⅲ. CIRCUIT DESCRIPTION
Ⅳ. MEASUREMENT RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (16)
참고문헌 신청
1. [학술대회논문] - W. Yang / 1999 / An integrated 800×600 CMOS imaging system / ISSCC Dig. Tech. Papers : 304 ~ 305
2. [학술지(정기간행물)] - D. Lee and G. Han / 2007 / High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers / ELECTRONICS LETTERS 43 : 1362 ~ 1364
3. [학술지(정기간행물)] - Y. Chae / 2011 / A 2.1 Mpixels, 120 frame/s CMOS image sensor with column-parallel WΣ ADC architecture / IEEE J. Solid-State Circuits 46 (1) : 236 ~ 247
4. [학술대회논문] - Y. Nitta / 2006 / High-speed digital double sampling with analog CDS on column parallel ADC architecture for low-noise active pixel sensor,” / ISSCC Dig. Tech. Papers : 500 ~ 501
5. [학술지(정기간행물)] - S. Yoshihara / 2006 / A 1/1.8-inch 6.4Mpixel 60 frames/s CMOS image sensor with seamless mode change / IEEE J. Solid-State Circuits 41 (12) : 2998 ~ 3006
2. [학술지(정기간행물)] - D. Lee and G. Han / 2007 / High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers / ELECTRONICS LETTERS 43 : 1362 ~ 1364
3. [학술지(정기간행물)] - Y. Chae / 2011 / A 2.1 Mpixels, 120 frame/s CMOS image sensor with column-parallel WΣ ADC architecture / IEEE J. Solid-State Circuits 46 (1) : 236 ~ 247
4. [학술대회논문] - Y. Nitta / 2006 / High-speed digital double sampling with analog CDS on column parallel ADC architecture for low-noise active pixel sensor,” / ISSCC Dig. Tech. Papers : 500 ~ 501
5. [학술지(정기간행물)] - S. Yoshihara / 2006 / A 1/1.8-inch 6.4Mpixel 60 frames/s CMOS image sensor with seamless mode change / IEEE J. Solid-State Circuits 41 (12) : 2998 ~ 3006
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