지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 569 - 572 (4page)
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초록· 키워드
오류제보하기
As power consumption becomes one of the most important characteristics, the number of clocks increases to implement low power features efficiently in modern mobile AP designs. In this circumstance, asynchronous design and “Clock Domain Crossing (CDC)” verification are becoming one of the biggest challenges on over 100M gate SOC designs. Tricky setup due to complex clock relations and complex design, long run time, huge number of false-errors and various operation modes are the known problems of top-level CDC verification. Among the difficulties, 70,000 ~ 100,000 issues after CDC analysis in an over 100M gate SOC overwhelm designers with its huge volume. This paper presents a comprehensive study on “huge number of false-errors after CDC analysis,” and shows the categories of all types of false-errors and causes, like wrong setups, unidentified static signals, broken asynchronous interfaces etc., which are contributing to a huge number of false-errors. Also, knowledge based solutions for known culprits are presented. It is shown that 95% of false-errors could be eliminated efficiently with the proposed knowledge-based solutions through our 3 case-studies.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. REASONS OF MAJOR CDC FALSE-ERRORS
Ⅲ. CASE-STUDIES
Ⅳ. CONCLUSION
Ⅴ. REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000730440