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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 459 - 462 (4page)
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초록· 키워드
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Three-dimensional (3D) integration offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. Stacked mesh 3D NoC architecture was proposed to take advantage of the intrinsic capability of reducing the wire length in 3D ICs. However, this architecture still exacerbates the on-chip power density and router cost. In this paper, we propose a novel hybridization scheme for inter-layer communication using efficient 5-input routers to enhance the overall system power, performance, and area characteristics of the existing Hybrid NoC-Bus 3D mesh architecture. By defining a rule for routing algorithms called LastZ, the proposed area-efficient architecture decreases the overall average hop count of a NoC-based system compared to the existing architectures. We further improve this design by proposing partial-LastZ-based 3D NoC-bus hybrid architecture to provide adaptivity for implementing congestion-aware and fault-tolerant inter-layer routing algorithms. Extensive quantitative experiments demonstrate up to 16% performance improvement compared to the full LastZ-based 3D NoC-bus hybrid architecture and around 20% area reduction compared to the typical hybrid NoC-Bus 3D mesh architecture.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. LASTZ ROUTING POLICY
Ⅲ. LASTZ-BASED HYBRIDIZATION ARCHITECTURE
Ⅳ. PARTIAL-LASTZ-BASED 3D NOC ARCHITECTURE
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSION AND FUTURE WORK
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000730162