지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 401 - 404 (4page)
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초록· 키워드
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The shortened RS code is traditionally decoded based on the standard decoding process by padding zero symbols. As additional cycles are redundantly taken to deal with the zero symbols, the processing latency of the shortened code is almost the same as that of the mother RS code from which the shortened code is derived. A new architecture is proposed in this paper to decrease the processing latency to the codeword length of the shortened RS code, which can be implemented at the cost of small additional hardware resources. The additional hardware complexity is minimized by reutilizing the hardware resources resident in the adjacent block. Experimental results show that the proposed method leads to a significant reduction of the overall latency. For the RS (32, 24) code, the overall processing latency is reduced by 85.2% and 33.6% compared to the conventional and the previous work, respectively. Moreover, the additional hardware complexity of the proposed method is smaller than those of the previous architectures.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. RS DECODING
Ⅲ. PROPOSED RS DECODER
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000730011