지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 231 - 234 (4page)
이용수
초록· 키워드
오류제보하기
This paper describes the design of a 10Gb/s output driver offering a constant output voltage swing level over process, voltage and temperature (PVT) variations. Output voltage swing level can be controlled by MOS resistances in the final output driver stage. The proposed architecture employs replica output driver to compensate output voltage swing level. The gate voltage of PMOS/NMOS in the main output driver, which is generated by comparing voltage swing level of the replica driver with the desired output swing level, makes output driver voltage swing level to be constant by adjusting MOS resistances in the final stage of the output driver. The low swing output driver can be achieved by the proposed architecture; it reduces the power dissipation by reducing the voltage swing on the load. The proposed output driver is implemented using 65-㎚ CMOS process and operates at 10Gbps data rate over 30cm FR4-model.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. MOS RESISTANCE CHARACTERISTICS
Ⅲ. CIRCUIT IMPLEMENTATION
Ⅳ. SIMULATION RESULTS
Ⅴ. CONCLUSION
REFERENCES
참고문헌 (0)
참고문헌 신청이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2014-569-000729581