지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 227 - 230 (4page)
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초록· 키워드
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A 5Gb/s four-level pulse amplitude modulation (4-PAM) transceiver front-end for low-power memory interface is proposed. Since the most power-consuming blocks in high-speed link front-end are drivers, and equalizers, in this work, we have used 4-PAM voltage mode driver to reduce the power consumption of driver and equalizer. Moreover, an analysis to minimize voltage mode driver power consumption is presented. In order to eliminate the reflection in a multi-drop bus, an impedance-matched bi-directional multi-drop bus has implemented. Simulation results show the proposed transceiver front-end has power efficiency of 1.7 ㎽/Gbps. Circuit design and simulation were done in 0.13-㎛ CMOS technology.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE
Ⅲ. IMBM CHANNEL CHARACTERISTICS
Ⅳ. CIRCUIT IMPLEMENTATION
Ⅴ. SIMULATION RESULTS
Ⅵ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000729576