지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 223 - 226 (4page)
이용수
초록· 키워드
오류제보하기
In this paper, we propose a high-speed support vector machine (SVM) circuit for driver assistance system (DAS). By adopting a parallel architecture with pipeline, the circuit can provide real-time processing with a large amount of operations. The circuit can support both linear and non-linear SVM types by unifying their algorithms and architectures. The circuit size is minimized by sharing most of the resources required in the computation for both SVM types. We described the proposed high-speed SVM circuit using Verilog HDL and implemented an MPW chip using a 65㎚ standard cell library for silicon verification. Since the circuit can process 92 640x480 image frames per second, assuming three cameras installed on the vehicle, it can be used to provide real-time pedestrian and vehicle detection for DAS.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. BRIEF REVIEW OF SVM ALGORITHMS
Ⅲ. PROPOSED ARCHITECTURE
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000729561