지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.3
- 발행연도
- 2012.9
- 수록면
- 293 - 296 (4page)
이용수
초록· 키워드
오류제보하기
Abstract?SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a systemon-a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. IEEE TEST STANDARDS
Ⅲ. HIERARCHICAL TEST ARCHITECTURE
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (5)
참고문헌 신청
1. [학술지(정기간행물)] - Sunghoon Chun / 2007 / A New Scan Chain Fault Simulation for Scan Chain Diagnosis / Journal of Semiconductor Technology and Science 7
2. [학술지(정기간행물)] - J.-F. Li / 2002 / A hierarchical test methodology for systems on chip / Micro, IEEE 22
3. [기타자료] - IEEE Computer Society Test Technology Technical Committee / 1990 / IEEE Standard Test Access Port and Boundary-Scan Architecture
4. [기타자료] - IEEE Computer Society / 2005 / IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits
5. [기타자료] - IEEE Computer Society / 2010 / IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture
2. [학술지(정기간행물)] - J.-F. Li / 2002 / A hierarchical test methodology for systems on chip / Micro, IEEE 22
3. [기타자료] - IEEE Computer Society Test Technology Technical Committee / 1990 / IEEE Standard Test Access Port and Boundary-Scan Architecture
4. [기타자료] - IEEE Computer Society / 2005 / IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits
5. [기타자료] - IEEE Computer Society / 2010 / IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture
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