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The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.
목차
1. Introduction
2. Previous Research
3. Hexagonal Layout and SemiconductorHexagonal Layout
4. Simulation Analysis
5. Conclusions
References
참고문헌 (30)
참고문헌 신청
1. [보고서] - Campbell, E. / 2000 / 300 mm factory layout and material handling modeling : phase II report
2. [학술지(정기간행물)] - Chen, H. / 1988 / Empirical evaluation of a queueing network model for semiconductor wafer fabrication / Operations Research 36 (2) : 202 ~ 215
3. [학술지(정기간행물)] - Connors, D. P. / 1996 / Queueing network model for semiconductor manufacturing / IEEE Transactions on Semiconductor Manufacturing 9 (3) : 412 ~ 427
4. [학술지(정기간행물)] - Chung, J. / 2007 / The integrated room layout / IEEE Transactions on Semiconductor Manufacturing 20 (4) : 517 ~ 527
5. [기타자료] - Chung, J. / / Layout Design with Hexagonal Floor Plans and Material Flow Patterns / International Journal of Production Research
2. [학술지(정기간행물)] - Chen, H. / 1988 / Empirical evaluation of a queueing network model for semiconductor wafer fabrication / Operations Research 36 (2) : 202 ~ 215
3. [학술지(정기간행물)] - Connors, D. P. / 1996 / Queueing network model for semiconductor manufacturing / IEEE Transactions on Semiconductor Manufacturing 9 (3) : 412 ~ 427
4. [학술지(정기간행물)] - Chung, J. / 2007 / The integrated room layout / IEEE Transactions on Semiconductor Manufacturing 20 (4) : 517 ~ 527
5. [기타자료] - Chung, J. / / Layout Design with Hexagonal Floor Plans and Material Flow Patterns / International Journal of Production Research
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UCI(KEPA) : I410-ECN-0101-2013-530-003637465