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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.2
- 발행연도
- 2012.6
- 수록면
- 168 - 174 (7page)
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초록· 키워드
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This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 ㎚ CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED GLOBAL ON-CHIP INTERCONNECT SCHEME
Ⅲ. COMPARISON AND DISCUSSION
Ⅳ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (12)
참고문헌 신청
1. [학술지(정기간행물)] - R. Ho / 2001 / The future of wires / Proc. IEEE : 490 ~ 504
2. [학술지(정기간행물)] - Kwan Young Kim / 2010 / Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 10 (2) : 134 ~ 142
3. [학술지(정기간행물)] - Hye Won Kim / 2011 / Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 11 (1) : 15 ~ 22
4. [학술지(정기간행물)] - P. Larsson-Edefors / 2000 / Investigation on maximal throughput of a CMOS repeater chain / IEEE Trans. Circuits and Systems-I, Fundamental Theory and Application 47 (4) : 602 ~ 606
5. [단행본] - H. B. Bakoglu / 1990 / Circuits, interconnections and Packaging for VLSI / Addison-Wesley
2. [학술지(정기간행물)] - Kwan Young Kim / 2010 / Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 10 (2) : 134 ~ 142
3. [학술지(정기간행물)] - Hye Won Kim / 2011 / Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 11 (1) : 15 ~ 22
4. [학술지(정기간행물)] - P. Larsson-Edefors / 2000 / Investigation on maximal throughput of a CMOS repeater chain / IEEE Trans. Circuits and Systems-I, Fundamental Theory and Application 47 (4) : 602 ~ 606
5. [단행본] - H. B. Bakoglu / 1990 / Circuits, interconnections and Packaging for VLSI / Addison-Wesley
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