지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 630 - 633 (4page)
이용수
초록· 키워드
오류제보하기
Boundary scan, also known as the IEEE 1149.1, or JTAG standard appears to be the most successful test standard ever approved by the IEEE. Initially targeting board-level testing for digital circuits, this standard has now been adopted by industry for use in most large IC chips and has been used to access many other applications, including power management, clock control debugging, verification and chip reconfiguration. Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods cannot be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register for multiple clocks testing within the design of multiple scan chains. The proposed Clock Group Register has the function of grouping clocks. By adding Clock Group Register to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scanin ports and out ports. Through our experiments, the effectiveness of Clock Group Register is proved. With this, it is possible to test more complicated designs that have high density with a little effort.
목차
Abstract
1. Introduction
2. Sphere of Proposed Clock Group Register
3. Verification of Clock Group Register and Experimental Results
4. Conclusions
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001759692