지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2009.11
- 수록면
- 208 - 211 (4page)
이용수
초록· 키워드
오류제보하기
As the VLSI technologies scale down to the nanometer regime, the circuit design and verification processes have become more and more complex and a reliable operation of VLSI becomes sensitive to the PVT (Process, Voltage, and Temperature) variations. Therefore, the LSI test only before the shipment to screen out the initial failures has been insufficient to ensure the reliable in-field operation of LSI.
In this paper, we propose an SoC platform with on-chip web interface to realize an in-field LSI testing and an easy access to the on-chip LSI monitoring circuits such as scan registers, temperature sensors, and so on. We can control the on-chip monitoring systems through the web interface, and can monitor the LSI correct operations from remote locations using the proposed platform. Therefore, the proposed SoC platform realizes the LSI functionality monitoring even after the shipment and can test the in-field operation of LSI. This platform consists of 16-bit CPU, 64K words of instruction/data memory, and 10Base-T ethernet interface. A preliminary version of the proposed platform was implemented on 0.18μm standard CMOS process. The area overhead is 8.44mm2 on 0.18μm process, and is estimated to scale down to about 1mm<SUB>2</SUB> on 65nm process.
In this paper, we propose an SoC platform with on-chip web interface to realize an in-field LSI testing and an easy access to the on-chip LSI monitoring circuits such as scan registers, temperature sensors, and so on. We can control the on-chip monitoring systems through the web interface, and can monitor the LSI correct operations from remote locations using the proposed platform. Therefore, the proposed SoC platform realizes the LSI functionality monitoring even after the shipment and can test the in-field operation of LSI. This platform consists of 16-bit CPU, 64K words of instruction/data memory, and 10Base-T ethernet interface. A preliminary version of the proposed platform was implemented on 0.18μm standard CMOS process. The area overhead is 8.44mm2 on 0.18μm process, and is estimated to scale down to about 1mm<SUB>2</SUB> on 65nm process.
목차
Abstract
I. INTRODUCTION
II. CONCEPT OF THE PROPOSED PLATFORM
III. ARCHITECTURE OF THE PROPOSED PLATFORM
IV. EXPERIMENTAL RESULTS
V. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
SoC(System-on-Chip)
TTA 저널
2004 .01
-
New PLatform에 필요한 SoC
대한전자공학회 워크샵
2007 .03
-
[대특집-SOC(System On Chip) 기술]SOC 기술동향
전자공학회지
2002 .01
-
[대특집-SOC(System On Chip) 기술]SOC 구현 기술 동향
전자공학회지
2002 .01
-
SoC Platform Design with Multi-Channel Bus Architecture
대한전자공학회 ISOCC
2008 .11
-
[대특집-SOC(System On Chip) 기술]SOC 테스트 기술 동향
전자공학회지
2002 .01
-
[대특집-SOC(System On Chip) 기술]SOC CAD 기술 동향
전자공학회지
2002 .01
-
[대특집-SOC(System On Chip) 기술]SOC를 위한 효율적인 IP 재활용 방법론
전자공학회지
2002 .01
-
[대특집-SOC(System On Chip) 기술]IP 기반 SOC 설계 기술 동향
전자공학회지
2002 .01
-
[특집:SoC Platform 설계기술]SoC 설계 방법의 최근 동향
전자공학회지
2003 .09
-
[특집:SoC Platform 설계기술]Design Guidelines for Mixed-Signal SoC
전자공학회지
2003 .09
-
Design and Development of Open NMS Interface
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2005 .07
-
IT-SoC
TTA 저널
2005 .01
-
[특집:SoC Platform 설계기술]SoC를 위한 통신망 설계 동향
전자공학회지
2003 .09
-
Effective Verification Environment using SoC Platform
대한전자공학회 ISOCC
2006 .10
-
개선된 SoC에 관한 연구
대한전자공학회 학술대회
2016 .11
-
[대특집-SOC(System On Chip) 기술]특집 편집기
전자공학회지
2002 .01
-
SoC 가상화 플랫폼을 이용한 SoC 구조 개발 및 검증 방법
전자공학회논문지
2017 .11
-
IT SOC 기술
전자공학회지
2009 .02
-
국내 SOC 리포트카드 작성 지원을 위한 SOC 정보시스템 시범 구축 연구
한국산학기술학회 논문지
2017 .02
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2013-569-001482625