지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 262 - 265 (4page)
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초록· 키워드
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This paper describes the design of AdaBoost classifier circuit using the Haar-like features for the automobile applications. In order to extract the features of an object, the proposed circuit uses the Haar-like feature extraction method. The proposed circuit extracts a total of 200 Haar-like features per sliding window. The extracted features are provided to the AdaBoost classifier circuit in order to determine whether the object is the expected one or not. A 48×96 or 64×64 sliding window with 10 window strides is used in the proposed circuit for the efficient pattern recognition. In order to increase the processing speed, the proposed circuit adopts the parallel architecture and it can process two sliding windows at the same time. We described the proposed high-performance pattern recognition circuit using Verilog HDL and synthesized the gatelevel circuit using the 130nm standard cell library. The synthesized circuit consists of 428,397 gates and its maximum operating frequency is 203MHz. 148 240×8-bit, 107 192×710-bit, and one 200×102-bit SRAMs are used in the proposed circuit. The circuit processes 38.4 640×480 image frames per second, assuming ten different levels of resolution for each frame, i. e. nine successive scaling down for each 640×480 image frame.
목차
Abstract
I. INTRODUCTION
II. PATTERN RECOGNITION METHOD
III. PROPOSED PATTERN RECOGNITION CIRCUIT
IV. EXPERIMEMTAL RESULTS
V. CONCULSION
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UCI(KEPA) : I410-ECN-0101-2013-569-001474898