지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 135 - 138 (4page)
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초록· 키워드
오류제보하기
Via-first through-silicon vias (TSVs) are manufactured through bulk silicon and connected to landing pads in metal layers. Landing pads are made large enough to cover the top surface of TSVs entirely so that TSV-to-landing pad connections become invulnerable to uncertainties such as misalignment between TSVs and landing pads. Large landing pads, however, could lead to metal density mismatch problems, which result in nonuniform topography. In this paper, we investigate the metal density mismatch problem in 3D ICs and propose a TSV density-driven 3D global placement algorithm to minimize topography variation in 3D IC layouts. The experimental results show that we achieve 1.86× improvement in the range of metal 1 densities and 2.10× improvement in the maximum metal 1 density gradient with just 2.3% wirelength overhead. We also present additional studies such as the impact of landing pad size on metal density.
목차
Abstract
I. INTRODUCTION
II. MOTIVATION
III. TSV DENSITY-DRIVEN 3D GLOBAL PLACEMENT
IV. EXPERIMENTAL RESULTS
V. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001474585