지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 127 - 130 (4page)
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초록· 키워드
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Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. Through Silicon Via (TSV) formation is one of the key enabling technologies for 3D ICs. While TSVs provide vertical connections between different dies for higher performance, they suffer from random open defects and thermo-mechanical stress. The potential yield loss can significantly increase the mass production cost, which in turn affects the profitability of 3D ICs. To address the TSV reliability issues, double TSV, shared spare TSV and TSV fault tolerant unit (TFU) techniques have been developed. In this paper, we briefly review them and use 3D clock networks as a vehicle to compare their effectiveness and overhead.
목차
Abstract
I. INTRODUCTION
II. TSV FAULT-TOLERANT MECHANISMS
III. EXPERIMENTAL RESULTS
IV. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001474565