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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 92 - 95 (4page)
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초록· 키워드
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The time spent to design mixed hardware-software embedded systems is proportioned to their complexity. We present a highly efficient method that make use of simulators in order to find a pareto-solution between execution time and hardware area for mixed hardware-software embedded systems. Our method generates the minimum possible number of mappings in order to reduce the number of simulations. The exploration starts with two system mappings as initial pareto-solution. Then it repeats three steps, the generation of mappings, the simulation of generated mappings, and the update of the pareto-solution with the results of simulations. The experimental results show that our method is notably efficient and is able to find a pareto-solution with few errors compared to the complete search method.
목차
Abstract
I. INTRODUCTION
II. SIMULATION-BASED DESIGN SPACE EXPLORATION
III. PARETO-UPDATE SEARCH
IV. A CASE STUDY ON MPEG-4 DECORDER APPLICATION
V. CONCLUSION
ACKNOWLEDGMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001474474