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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 32 - 35 (4page)
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초록· 키워드
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This paper proposes a low-phase-noise ring-VCObased frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34GHz with reference signals of 528MHz was ?o113 dBc/Hz.
목차
Abstract
I. INTRODUCTION
II. CONVENTIONAL PULSE INJECTION LOCKING
III. PROPOSED ILFM WITH NEW PULSE GENERATION TECHNIQUE
IV. MEASUREMENT RESULT
V. CONCLUSION
ACKNOWLEDGMENTS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001474323