지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 5 - 8 (4page)
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초록· 키워드
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This paper describes a 60 GHz high gain power amplifiers (PA) designed in a 0.18-μm SiGe BiCMOS technology. It consists of four cascode stages with inter-stage matching implemented by the conductor-backed coplanar waveguide (CBCPW) structures and metal-insulator-metal (MIM) capacitors. A double-stub low Q input matching network is design to achieve wideband input matching. Since one of double-stub is open stub, the S11 can easily be tuned by trimming after fabrication. Load-pull simulation generates the optimal load impedance. A wideband harmonic rejection ESD is introduced to simultaneously reject the harmonics and achieve ESD protection. Simulation result shows that the maximum gain is 35.4 dB with 3 dB bandwidth 55-69 GHz. The S11 is ¡-10 dB in the 50-80 GHz. The output P1dB is 6.7 dBm and the saturated output power Psat is 8.9 dBm. The peak PAE is 12.8%. The chip size is 1050×280 um2. It consumes 60mW from a 1.8V supply.
목차
Abstract
I. INTRODUCTION
II. MM-WAVE PASSIVE AND ACTIVE COMPONENTS
III. SIMULATION RESULTS
IV. CONCLUSION
ACKNOWLEDGMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001474252