지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.11 No.3
- 발행연도
- 2011.9
- 수록면
- 182 - 189 (8page)
이용수
초록· 키워드
오류제보하기
In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of rn.v TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting Ge-AI<SUB>x</SUB>Ga<SUB>1-x</SUB>AsGe system has been optimized by simulation in terms of aluminum (AI) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (UP) logic technology can be achieved by the proposed device. The optimum AI composition turned out to be around 20% (x=0.2).
목차
Abstract
I. INTRODUCTION
II. STRATEGIES IN DEVICE DESIGN
III. SIMULATION RESULTS
IV. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001235633