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논문 기본 정보

자료유형
학술저널
저자정보
Priyanka Malik (Delhi University) R.S. Gupta (Maharaja Agrasen Institute of Technology) Rishu Chaujar (Delhi Technological University) Mridula Gupta (Delhi University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.11 No.3
발행연도
2011.9
수록면
169 - 181 (13page)

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초록· 키워드

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In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: gm<SUB>1</SUB>, gm<SUB>2</SUB>, gm<SUB>3</SUB>, and figure-of-merit (FOM) metrics; V<SUB>IP2</SUB>, V<SUB>IP3</SUB>, IIP3 and I-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X<SUB>j</SUB>) or negative junction depth (NJD) have been examined for GME- TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

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Abstract
I. INTRODUCTION
II. FABRICATION FEASIBILITY OF GME-TRC MOSFET
III. STRUCTURE DESCRIPTION
IV. MODEL FORMULATION
V. RESULTS AND DISCUSSION
VI. CONCLUSIONS
REFERENCES

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UCI(KEPA) : I410-ECN-0101-2013-569-001235628