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논문 기본 정보

자료유형
학술저널
저자정보
Yoonjin Kim (Sookmyung Women’s University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.11 No.4
발행연도
2011.12
수록면
318 - 328 (11page)

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초록· 키워드

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Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/ power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. RELATED WORKS
Ⅲ. PRELIMINARIES
Ⅳ. MOTIVATION
Ⅴ. HIERARCHICAL MULTIPLEXINGINTERCONNECTION STRUCTURE
Ⅵ. EXPERIMENTS
Ⅶ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES

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UCI(KEPA) : I410-ECN-0101-2013-569-001351403